The present invention is directed to automatic circuit testing and particularly to the data and timing circuits for such testers.
The operation of automatic circuit testers can be thought of as the application, at some clock rate, of vectors to a group of nodes in a device under test. A "vector" is the ordered list of the binary values to be applied to all of the nodes within a clock period of the tester. Applied in this case can mean either impressing upon a node the particular binary value or testing the node for that value. There are very many performance criteria for automatic circuit testers, but the major performance criteria are the number of nodes that a tester can test simultaneously and the speed at which it can apply vectors to those nodes. The latter criterion, namely, speed, is the one to which the present invention is directed.
As the speed of integrated circuits has increased, so has the speed requirements of the testers used to test them. However, it has now become apparent that testers of conventional architecture have significant speed limitations. A large part of this limitation stems from the complexity exhibited by conventional tester architecture. Tester architectures differ, but the typical tester includes a large memory device for each tester terminal, or "pin." Each location in the memory contains the data to be applied to the tester terminal at a different clock period.
Also included in the typical pin electronics is a formatter, which translates the memory data either into signals applied to the tester pin (driving) or into comparisons made with the signals present on the tester pin (sensing). For proper operation, the pin electronics further requires timing information. The memories contain the data to be applied to the tester terminals within a given clock period, while the timing information indicates when, within a clock period, the data are to be applied. The formatter converts the data and the timing information into a signal of the proper value having the proper timing within a clock period.
The circuitry for performing this conversion varies greatly from tester to tester, but it typically is fairly complex and includes counters, programmable delay lines, or combinations of these. At the high data rates required of modern testers, it is difficult to arrange all the circuitry so that various signals track each other accurately, and this difficulty increases with speed so as ultimately to place a limitation on the speed at which a tester can operate.